ISSI 8GB DDR4 SDRAM
ISSI 8GB DDR4 SDRAM are high-speed dynamic random-access memory devices with data transfer rates up to 3200Mbps. The 8GB DDR4 SDRAM is internally organized with eight banks. Two configurations are available: either two bank groups, each with four banks for x16, or four bank groups, each with four banks for x8. The DDR4 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture combines an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the ISSI DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.Features
- 1.2V, 2.5V VPP VDD = VDDQ
- Up to 3200Mbps high-speed data transfer rates with system frequency
- Data integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
- DRAM access bandwidth
- Separated IO gating structures by Bank Groups
- Self Refresh Abort
- Fine Granularity Refresh
- Signal Synchronization
- Write Leveling via MR settings
- Read Leveling via MPR
- Reliability and Error Handling
- Command/Address Parity
- Data bus Write CRC
- MPR readout
- Boundary Scan
- Speed Grade (CL-TRCD-TRP)
- 2400Mbps/17-17-17 (-083T)
- 2666Mbps/19-19-19 (-075V)
- 2933Mbps/21-21-21 (-068Y)
- 3200Mbps/22-22-22 (-062AA)
- Programmable functions
- Output Driver Impedance (34/48)
- CAS Write Latency (9/10/11/12/14/16/18/20)
- Additive Latency (0/CL-1/CL- 2)
- CS# to Command Address (3/4/5/6/8)
- Burst Type (Sequential/Interleaved)
- Write Recovery Time (10/12/14/16/18/20/24)
- Read Preamble (1T/2T)
- Write Preamble (1T/2T)
- Burst Length (BL8/BC4/BC4 or 8 on the fly)
- Configurations
- 512Mx16
- 1Gx8
- Package
- 96-ball BGA (10mm x 14mm, 0.8mm ball pitch) for x16
- 78-ball BGA (10mm x 14mm, 0.8mm ball pitch) for x8
- Signal Integrity
- Internal VREFDQ Training
- Read Preamble Training
- Gear Down Mode
- Per DRAM Addressability
- Configurable DS for system compatibility
- Configurable On-Die Termination
- Data bus inversion (DBI)
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240Ω ±1%)
- Power Saving and efficiency
- POD with VDDQ termination
- Command/Address Latency (CAL)
- Maximum Power Saving
- Low power Auto Self Refresh (LPASR)
- Temperature Grades
- 0°C to +85°C Commercial
- -40°C to +85°C Industrial
- -40°C to +85°C Automotive, A1
- -40°C to +105°C Automotive, A2
Applications
- Telecom and networking
- SDN, NFV
- Access and aggregation nodes
- Switches and routers
- Packet optical transport
- Network storage (PON OLT, DSLAM, CMTS, Wireless)
- Automotive
- Infotainment
- Driver information systems
- Industrial
- Human-machine interface
- Embedded computing
發佈日期: 2020-07-14
| 更新日期: 2024-10-28
