PI6CB33401 & PI6CB33402 PCIe Clock Buffers

Diodes Incorporated PI6CB33401 and PI6CB33402 4-Output PCIe Clock Buffers use a proprietary Phase-Locked Loop (PLL) design to achieve very low jitter. A low-jitter clock is an integrated circuit that produces a timing signal for use in synchronizing a system's operation. The jitter, or irregular time delay, meets Peripheral Component Interconnect Express Gen1/Gen2/Gen3/Gen4/Gen5 requirements. Other than PCIe 100MHz support, these devices also support Ethernet applications with 50MHz, 125MHz, and 133.33MHz via SMBus. On-chip termination can save 16 external resistors and make layout easier. The individual OE pin for each output provides easier power management.