Terasic Technologies Heterogeneous Extensible Robot Open Platform
Terasic Technologies Heterogeneous Extensible Robot Open (HERO) Platform is a low-power, high-performance, mini-sized system platform solution optimized for intelligent robotics, such as service robots, medical robots, and self-driving vehicles. In this platform, the CPU acts as a control center, paired with field-programmable gate arrays (FPGAs) to provide efficient performance. The HERO system features an Intel® Core™ processor with an Altera Arria 10 GX Series 1150 FPGA as a heterogeneous accelerator.
The Terasic HERO platform includes a customized board support package (BSP) that supports OpenCL-based flow development, providing a friendly programming interface for a wide range of algorithms and software programming for software engineers. For a customized system to support OpenCL flow, the platform requires FPGA hardware to provide complete data and control paths other than compatible software from the host. The OpenCL kernel can then be loaded dynamically in real-time and run on the FPGA platform. To support OpenCL Flow, the full FPGA BSP has been ported to the HERO platform and is available as an integral part of the HERO software development kit (SDK). The FPGA logic part of the existing HERO SDK BSP includes a high-speed communication interface PCIe IP core, a memory DMA controller, an off-chip high-speed memory DDR4 interface, and a communication interface with the FPGA internal module.
Features
- CPU system
- Intel® Core™ processor
- 256GB RAID configuration
- 8GB memory type (DDR4-2133 1.2V SO-DIMM)
- USB Type-C™ configuration: 1x port, supports Thunderbolt 3 (40Gbps) USB 3.1 Gen 2 (10Gbps) and DP 1.2
- Graphic output: HDMI 2.0a; USB-C (DP1.2)
- 10/100/1000 integrated LAN
- Integrated Wi-Fi®: Intel® wireless-AC 8265 + BLUETOOTH® 4.2
- USB 3.0 configuration: 2x host ports
- FPGA system
- Altera Arria® 10 GX FPGA (10AX115S2F45I1SG)
- FPGA configuration
- Onboard USB Blaster II or JTAG header for FPGA programming
- Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
- Installed software
- Linux Ubuntu 16.04
- Intel® FPGA Runtime for OpenCLTM Linux x86-64
- Intel® OpenVINO Toolkit with FPGA support
- Memory
- 256MB flash
- 2GB DDR4 (2400 x64)
- Communication and expansion
- PCI Express (PCIe) x8 edge connector
- USB 3.0 host/device
- Gigabit Ethernet
- UART
- CAN
- SPI
- I2C
- General user input/output
- 8x LEDs
- 3x pushbuttons
- 8x DIP switches
- Onboard clock
- 50/100/125MHz fixed clock
- Programmable clock generator
- System monitor and control
- Temperature Sensor
- Power Monitor
Applications
- Drones
- Service robots
- Medical robots
- Self-driving vehicles
Videos
Kit Contents
Case Layout
Case Dimensions
Additional Resources
Development Software
Intel Distribution of OpenVINO™ Toolkit
Used to develop multiplatform computer vision solutions from smart cameras to robotics.
On The Board
Altera Arria® 10 GX FPGAs
Feature 96 full-duplex transceivers, supporting data rates of 17.4Gbps chip-to-chip.