Texas Instruments SN74LV8T164/SN74LV8T164-Q1 Parallel-Load Shift Register contains an 8-bit shift register with asynchronous clear (CLR) input and AND-gated serial inputs. The gated serial (A and B) inputs permit complete control over incoming data. A low at either input inhibits new data entry and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, determining the first flip-flop's state. The data at the serial inputs can be changed while CLK is low or high, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
