9DBV0231AKLF

Renesas Electronics
972-9DBV0231AKLF
9DBV0231AKLF

製造商：

說明：
時鐘緩衝器 PCIe BUFFER, 2 OUT GEN 1/2/3, LOW POWER

規格書:
ECAD模型:
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庫存：
0

您仍可購買此商品作為延期交貨訂單。

在途量:
490
預期3/4/2026
工廠前置作業時間：
12
週 工廠預計生產時間數量大於所顯示的數量。
最少： 1   多個： 1
單價:
HK$-.--
總價:
HK$-.--
估計關稅:

Pricing (HKD)

數量 單價
總價
HK$26.22 HK$26.22
HK$19.73 HK$197.30
HK$18.08 HK$452.00
HK$16.28 HK$1,628.00
HK$14.88 HK$3,720.00
HK$14.80 HK$7,252.00
HK$14.55 HK$14,259.00
HK$13.32 HK$39,160.80
HK$13.07 HK$70,447.30

商品屬性 屬性值 選擇屬性
Renesas Electronics
產品類型: 時鐘緩衝器
RoHS:  
2 Output
100 MHz
0 ps
VFQFPN-24
200 MHz
1.7 V
1.9 V
9DBV0231
0 C
+ 70 C
品牌: Renesas Electronics
安裝風格: SMD/SMT
運作供電電流: 25 mA
封裝: Tray
產品類型: Clock Buffers
原廠包裝數量: 490
子類別: Clock & Timer ICs
零件號別名: 9DBV0231
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所選屬性: 0

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CNHTS:
8542319090
CAHTS:
8542390000
USHTS:
8542390090
JPHTS:
854239099
TARIC:
8542399000
MXHTS:
8542399901
ECCN:
EAR99

計時IC解決方案

IDT is the world's leading provider of silicon timing devices (clock ICs) and offers the industry's broadest product portfolio of clock timing solutions for networking and communications, consumer, and computing applications. With the industry's largest market share, IDT is the only "one-stop-shop" for timing solutions, offering products from full-featured system solutions to simple clock building-block devices. Factory-programmable options and clock solution customization capabilities address unique customer requirements, while the lowest jitter and lowest power features set IDT apart from the competition.
Learn More

9FGVxxx/9DBVxxx PCI Express® Timers

Renesas Electronics 9FGVxxx/9DBVxxx PCI Express® Timers offer unprecedented power savings and integration for communications, computing, and consumer markets. 9FGVxxx synthesizers and 9DBVxxx buffers consume less than 50mW of power - less than one-tenth of the power required by previous solutions. The ultra-low power consumption reduces heat dissipation to ease cooling requirements in large-scale cloud computing applications. These clock synthesizers and buffers are available with either integrated or external termination on the differential outputs.

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