TMS320C5533AZAY05

Texas Instruments
595-S320C5533AZAY05
TMS320C5533AZAY05

製造商:

說明:
數位訊號處理器及控制器 - DSP、DSC Low power C55x fixed point DSP- up to 10

ECAD模型:
下載免費的庫載入器,為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。

庫存量: 115

庫存:
115 可立即送貨
工廠前置作業時間:
18 週 工廠預計生產時間數量大於所顯示的數量。
數量超過115會受到最小訂單要求的限制。
最少: 1   多個: 1
單價:
HK$-.--
總價:
HK$-.--
估計關稅:

Pricing (HKD)

數量 單價
總價
HK$44.72 HK$44.72
HK$34.20 HK$342.00
HK$31.56 HK$789.00
HK$28.61 HK$2,861.00
HK$26.80 HK$6,700.00
HK$26.63 HK$29,825.60
HK$26.39 HK$67,558.40

商品屬性 屬性值 選擇屬性
Texas Instruments
產品類型: 數位訊號處理器及控制器 - DSP、DSC
RoHS:  
DSPs
C55x
1 Core
50 MHz
BGA-144
64 kB
128 kB
1.05 V
TMS320C5533
SMD/SMT
- 10 C
+ 70 C
Tray
品牌: Texas Instruments
組裝國家: Not Available
擴散國: Not Available
原產國: PH
數據記憶體大小: 128 kB
開發套件: TMDX5535EZDSP
輸入/輸出電壓: 1.8 V to 3.3 V
指示類型: Fixed Point
接口類型: I2C, I2S, SPI, UART
濕度敏感: Yes
定時器/計數器數目: 3 x 32 bit
產品類型: DSP - Digital Signal Processors & Controllers
原廠包裝數量: 160
子類別: Embedded Processors & Controllers
電源電壓 - 最大值: 1.15 V
電源電壓 - 最小值: 998 mV
監察定時器: Watchdog Timer
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所選屬性: 0

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CAHTS:
8542310000
USHTS:
8542310035
TARIC:
8542319000
ECCN:
3A991.a.2

Processors

Texas Instruments Processors provide a comprehensive portfolio, proven software, and worldwide support, enabling industry-leading automotive and industrial solutions. TI is dedicated to advancing and optimizing today’s processors to meet tomorrow’s intelligence, performance, and cost requirements in automotive and industrial applications. Scalable hardware and software platforms with common code allow designers to seamlessly reuse and migrate across devices to protect future investment.

TMS320C553x Fixed-Point DSPs

Texas Instruments TMS320C553x Fixed-Point Digital Signal Processors (DSPs) are designed for low-power applications and based on the TMS320C55x DSPC55x DSP generation CPU processor core. The architecture achieves high performance and low power through increased parallelism and total focus on power savings. TI TMS320C553x DSPs support an internal bus structure composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle.