SN74LV2T74PWREP

Texas Instruments
595-SN74LV2T74PWREP
SN74LV2T74PWREP

製造商:

說明:
翻轉 BD9 SPIN EP SN74LV2T 74PWREP

ECAD模型:
下載免費的庫載入器,為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。

庫存量: 2,726

庫存:
2,726 可立即送貨
工廠前置作業時間:
12 週 工廠預計生產時間數量大於所顯示的數量。
最少: 1   多個: 1
單價:
HK$-.--
總價:
HK$-.--
估計關稅:

Pricing (HKD)

數量 單價
總價
HK$21.37 HK$21.37
HK$15.95 HK$159.50
HK$14.63 HK$365.75
HK$13.07 HK$1,307.00
HK$12.49 HK$3,122.50
HK$12.41 HK$12,410.00
HK$11.10 HK$33,300.00
HK$10.85 HK$65,100.00

商品屬性 屬性值 選擇屬性
Texas Instruments
產品類型: 翻轉
RoHS:  
LV
2 Circuit
Push-Pull
TSSOP-14
CMOS
- 8 mA
8 mA
1.8 V
5.5 V
SMD/SMT
- 55 C
+ 125 C
品牌: Texas Instruments
最高時鐘頻率: 66.2 MHz
輸入行數: 8 Input
輸出行數: 4 Output
產品類型: Flip Flops
系列: SN74LV2T74
原廠包裝數量: 3000
子類別: Logic ICs
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所選屬性: 0

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CAHTS:
8542390000
USHTS:
8542390090
TARIC:
8542319000
MXHTS:
8542399999
ECCN:
EAR99

SN74LV2T74/SN74LV2T74-Q1 Dual D-Type Flip-Flop

Texas Instruments SN74LV2T74/SN74LV2T74-Q1 Dual D-Type Flip-Flops contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.