SN65DSI83ZXHR

SN65DSI83/SN65DSI83-Q1 DSI-to-LVDS Bridge

Texas Instruments SN65DSI83/SN65DSI83-Q1 DSI-to-LVDS Bridge features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1Gbps per lane and a maximum input bandwidth of 4Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 packets. The device also converts the formatted video data stream to an LVDS output operating at pixel clocks operating from 25MHz to 154MHz, offering a Single-Link LVDS with four data lanes per link. The SN65DSI83/SN65DSI83-Q1 can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The device is also suitable for applications using 60fps 1366 × 768/1280 × 800 at 18bpp and 24bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces. The Texas Instruments SN65DSI83-Q1 devices are AEC-Q100 qualified for automotive applications.