CDCU877ARHARG4

Texas Instruments
595-CDCU877ARHARG4
CDCU877ARHARG4

製造商:

說明:
時鐘驅動器及分配 1.8v PLL Clock Drive r ALT 595-CDCU877AR ALT 595-CDCU877ARHAR

ECAD模型:
下載免費的庫載入器,為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。

供貨情況

庫存:
暫無庫存
工廠前置作業時間:
6 週 工廠預計生產時間。
最少: 2500   多個: 2500
單價:
HK$-.--
總價:
HK$-.--
估計關稅:
此產品免費航運

Pricing (HKD)

數量 單價
總價
完整捲(訂購多個2500)
HK$43.07 HK$107,675.00

備用包裝

製造商 元件編號:
包裝:
Reel, Cut Tape, MouseReel
供貨情況:
庫存量
價格:
HK$74.06
最小值:
1
製造商 元件編號:
包裝:
Reel, Cut Tape, MouseReel
供貨情況:
庫存量
價格:
HK$87.05
最小值:
1

相似產品

Texas Instruments CDCU877ARHAR
Texas Instruments
時鐘驅動器及分配 1.8v PLL Clock Drive r A 595-CDCU877ARHA A 595-CDCU877ARHAT

商品屬性 屬性值 選擇屬性
Texas Instruments
產品類型: 時鐘驅動器及分配
RoHS:  
VQFN-40
CDCU877A
- 40 C
+ 85 C
Reel
品牌: Texas Instruments
濕度敏感: Yes
安裝風格: SMD/SMT
產品: Clock Drivers
產品類型: Clock Drivers & Distribution
原廠包裝數量: 2500
子類別: Clock & Timer ICs
類型: Differential
每件重量: 104 mg
找到產品:
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至少選中以上一個核取方塊以顯示在此類別中類似的產品。
所選屬性: 0

                        
The G4 and E4 suffixes were added for ROHS conversion. The
G4 and E4 parts are exactly the same as the original parts
without the G4 or E4 suffix.

For lead-frame-based devices, the RoHS-compliant solution
is backward-compatible with lead-based processes; so the
same part is shipped regardless of whether a unique part
number or a standard part number is ordered.

Lead-frame-based unique part numbers will consist of the
standard part number plus a two-character suffix (usually
E4 or G4, sometimes E3, E6, G3 or G6).

"E" = RoHS-compliant

"G" = Green (RoHS-compliant and no Br/Sb)

Please contact a Mouser Technical Sales Representative for
further information.


5-1011-9

此功能需要啟用JavaScript。

CNHTS:
8542319000
CAHTS:
8542390000
USHTS:
8542390090
JPHTS:
8542390990
TARIC:
8542399000
MXHTS:
85423999
ECCN:
EAR99

CDCU877 Phase-Lock Loop Clock Driver

Texas Instruments CDCU877 Phase-Lock Loop Clock Driver is a high-performance, low-jitter, low-skew, zero-delay buffer. It distributes a differential clock input pair (CK, /CK) to 10 differential pairs of clock outputs (Yn, /Yn) and one differential pair of feedback clock outputs (FBOUT, /FBOUT). The clock outputs are controlled by the input clocks (CK, /CK), the feedback clocks (FBIN, /FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT, /FBOUT, are disabled while the internal PLL maintains its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE does not affect Y7, /Y7, as these are free-running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.