ADC3243IRGZT

Texas Instruments
595-ADC3243IRGZT
ADC3243IRGZT

製造商:

說明:
類比數位轉換器 - ADC 14-bit125 MSPS Analg to Digital Convert A 595-ADC3243IRGZR

ECAD模型:
下載免費的庫載入器,為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。

供貨情況

庫存:
暫無庫存
工廠前置作業時間:
18 週 工廠預計生產時間。
最少: 250   多個: 250
單價:
HK$-.--
總價:
HK$-.--
估計關稅:
此產品免費航運

Pricing (HKD)

數量 單價
總價
完整捲(訂購多個250)
HK$330.03 HK$82,507.50
1,000 報價

商品屬性 屬性值 選擇屬性
Texas Instruments
產品類型: 類比數位轉換器 - ADC
RoHS:  
ADC3243
SMD/SMT
VQFN-48
14 bit
Serial LVDS
125 MS/s
Pipeline
1.8 V
1.8 V
- 40 C
+ 85 C
Reel
品牌: Texas Instruments
ENOB - 有效位數: 11.9 Bit
特徵: Low Power
濕度敏感: Yes
功率消耗: 183 mW
產品類型: ADCs - Analog to Digital Converters
SFDR - 無雜波動態範圍 : 93 dB
SINAD - 訊號對雜訊和失真比率: 73.3 dB
原廠包裝數量: 250
子類別: Data Converter ICs
每件重量: 148.200 mg
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所選屬性: 0

此功能需要啟用JavaScript。

CNHTS:
8542319090
CAHTS:
8542390000
USHTS:
8542390030
JPHTS:
854239099
TARIC:
8542399000
MXHTS:
8542399999
ECCN:
3A991.c.4

ADC324x 14-Bit Analog-to-Digital Converters

Texas Instruments ADC324x 14-Bit Analog-to-Digital Converters (ADCs) are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS ADC family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

ADC3x高速12/14位元ADC

Texas Instrument ADC3x High-Speed 12/14-Bit Analog-to Digital Converters are a high-linearity, ultra-low power, dual-channel, 12 or 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converters (ADCs). These devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC3x supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12 or 14-bit output data from each channel.
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