ADC08DJ3200AAVT

Texas Instruments
595-ADC08DJ3200AAVT
ADC08DJ3200AAVT

製造商:

說明:
類比數位轉換器 - ADC 8-Bit Dual 3.2-GSPS or Single 6.4-GSPS A A 595-ADC08DJ3200AAV

ECAD模型:
下載免費的庫載入器,為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。
此產品可能需要額外文件才能出口至美國境外。

供貨情況

庫存:
暫無庫存
工廠前置作業時間:
18 週 工廠預計生產時間。
最少: 250   多個: 250
單價:
HK$-.--
總價:
HK$-.--
估計關稅:
此產品免費航運

Pricing (HKD)

數量 單價
總價
完整捲(訂購多個250)
HK$12,306.57 HK$3,076,642.50

商品屬性 屬性值 選擇屬性
Texas Instruments
產品類型: 類比數位轉換器 - ADC
付運限制:
 此產品可能需要額外文件才能出口至美國境外。
RoHS:  
ADC08DJ3200
SMD/SMT
FCBGA-144
8 bit
1 Channel/2 Channel
Serial
3.2 GS/s, 6.4 GS/s
Differential/Single-Ended
Folding Interpolating
1.1 V, 1.9 V
1.1 V
49.1 dB
- 40 C
+ 85 C
Reel
品牌: Texas Instruments
組裝國家: Not Available
擴散國: Not Available
原產國: Not Available
開發套件: ADC08DJ3200EVM
DNL - 差分非線性度: 0.15 LSB
ENOB - 有效位數: 7.8 Bit
特徵: Ultra High Speed
FPBW - 全功率頻寬: 8 GHz
INL - 積分非線性度: 0.3 LSB
濕度敏感: Yes
轉換器數: 2 Converter
Pd - 功率消耗 : 2.8 W
功率消耗: 2.8 W
產品類型: ADCs - Analog to Digital Converters
參考類型: Internal
基準電壓: 1.1 V
SFDR - 無雜波動態範圍 : 62 dB, 67 dB
關機: No Shutdown
SINAD - 訊號對雜訊和失真比率: 48.7 dB
原廠包裝數量: 250
子類別: Data Converter ICs
類型: S/H ADC
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所選屬性: 0

此功能需要啟用JavaScript。

CNHTS:
8542390000
CAHTS:
8542390000
USHTS:
8542390030
MXHTS:
8542399901
ECCN:
3A001.a.5.a.1

ADC08DJ3200 8-Bit RF-Sampling ADCs

Texas Instruments ADC08DJ3200 8-Bit, Dual 3.2GSPS or Single 6.4GSPS, RF-Sampling Analog-to-Digital Converters (ADC) directly sample input frequencies from DC to above 10GHz. The device offers dual-channel (up to 3200MSPS) and single-channel (up to 6400MSPS) modes. The Texas Instruments ADC08DJ3200 meets the demand of both high channel count or wide instantaneous signal bandwidth applications using programmable tradeoffs in channel count and Nyquist bandwidth which allows development of flexible hardware. In both dual- and single-channel modes with usable frequencies exceeding the –3dB point, using full-power input bandwidth (–3dB) of 8.0GHz, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The device uses JESD204B Serial Data Output Interface with a maximum lane rate of 12.8Gbps, and a reduced lane rate of 3.125Gbps is allowed on up to 16 lanes. System design is streamlined for phased array radar and MIMO communications through innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.